Electron transport in low dimensional structures is both of fundamental scientific interest and increasingly relevant to future advances in electronics. One-dimensional (1D) transport has been investigated with inherent 1D organic chains such as tetrathiafulvene-tetracyanoquinodimethane (TTF-TCNQ), carbon nanotubes, electron channels fabricated by dry etching or squeezed by a split gate in a field-effect transistor (FET), free-standing semiconductor nanowires (NWs) grown by laser ablation or vapor-liquid-solid (VLS) chemical reactions, and metal quantum point contacts formed by connecting two metal electrodes in a scanning tunneling microscope.
Semiconductor NWs along with carbon nanotubes and graphene have been identified as important directions for future electronics as the limits to traditional scaling of Si integrated circuits become more imminent. While nanowire (NW) research is still at an early stage, most efforts are concentrated on NW fabrication and are limited one-by-one assembly. VLS growth has both a variation of NW sizes, as a result of the varying sizes of the metal seeds used to initiate the growth, and a random placement as a result of the random variation in seed positions. For most VLS NWs, the growth is perpendicular to the substrate which makes contacting and organizing the NWs into circuits quite complex. There is increasing interest in integrating InAs or related III-V nanowire materials as the conduction channel in future generations of electronics as a consequence of the high mobility of these materials as compared with silicon. Current integrated circuits (ICs) have upwards of several billion transistors with transverse dimensions today as small as 15 nm, and spaced by about 15- to about 20-nm, so integration of III-V materials using any sort of post growth processing, involving one-by-one assembly of billions of nanowires, is problematic—i.e., the NWs should be grown in place for further processing into devices and circuits. The lattice mismatch between Si and InAs precludes a simple epitaxial solution without a very thick buffer layer, which is not feasible within the current IC scaling paradigm. It is clear that lithographically defined positioning and control of the NW size would be a preferable approach.
Previous work has shown the growth of GaAs NWs horizontally on a GaAs surface. This required a lattice-matched material system such as AlGaAs and was not applicable to technologically important systems such as InAs on Si. The process also required a sacrificial layer such as AlGaAs that could be oxidized after growth to isolate the NW from the substrate, introducing additional strain as a result of the oxidation.
Many groups have reported the growth of InAs NWs vertically from a Si(111) surface. However, this has many of the same issues as the VLS growth in terms of integrating large numbers of 3-terminal transistor devices in a well defined circuit. The Si(111) surface is not suitable for electronic integration which is uniquely available on the Si(001) surface as a result of the properties of the SiO2/Si(001) interface.
In homo- and hetero-epitaxy on a (001)-oriented Si substrate, NWs grow in <111> directions that are 35.3°-off from the substrate surface. This causes two major problems in their application to Si and III-V microelectronics; one is the random growth along four available <111> directions on (001) and the other is the fabrication of three-terminal contacts (source, gate, drain) to the NWs. There are eight equivalent <111> directions in silicon, four directed upward from a <100> surface, and four downward.
Meanwhile, tunnel field effect transistors (TFET) are emerging as potential replacements for CMOS transistors with low power consumption (lower dark current than possible with CMOS thermionic emission processes) with high on-currents. The most recent comparison of a 16-nm low-power Si FinFET CMOS (gate length 34 nm) with reported TFETs in both experiment and simulation are available from a recent review article. Although several TFETs with different materials and fabrication technologies have been reported, most of them are incompatible with future Si nanoelectronics as a result of degraded material qualities, complicated processing, and/or a substrate orientation incompatible with Si(001).
In principle, complementary TFET devices are feasible with an identical material by controlling either electrons or holes to tunnel at the reverse biased p-n junction or p-i-n structure with gate bias polarity. Because of the different effective masses and mobilities depending on carrier type, however, comparable performances for both p- and n-TFET from the same material that can outperform Si CMOS has yet to be achieved. 2-dimensional materials such as graphene and transition-metal dichalcogenides such as MoS2 need further study for industrial applications.
InxGa1-xAs and GexSn1-x nanowires have been proposed for n- and p-TFET respectively with the best performances demonstrated to date. They satisfy small direct bandgap and carrier effective mass for high tunneling probability and low resistance channel to increase on-state current, which are the primary conditions of complementary (C-) TFET to compete with Si CMOS. However, in previous studies they were grown separately on InP and Ge substrates, respectively, and cannot be accommodated into a single substrate and as a result cannot be integrated into Si CMOS microelectronics which exclusively uses Si(001) substrates. The reported TFETs had a conventional FET structure and were fabricated with standard FET processes.
Thus, a process and devices that overcome the problems described above would be a welcome addition to the art.